Pulse flops are among the most delay and power efficient state elements due to their economical use of clock devices and clock power. However, pulse quality is critical to pulse flop effectiveness. A pulse flop is transparent and vulnerable to race-through failure during the pulse window. Pulse width variation expands the minimum time flop data must be held and the number of delay padding circuits that must be added to short logic paths. Minimum hold time elements can number in the hundreds of thousands for modern semiconductor designs.
Conventional pulse generators use a delay chain. The delay chain switches with the clock twice per clock cycle and is a large consumer of active power. The consumption is worse still when the delay chain is part of the individual flop. As such, delay chain power detracts from the efficiency of pulse flops.